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| T6L24 TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic T6L24 Source Driver for TFT LCD Panels The T6L24 is a 240-channel-output source driver for TFT LCD panels. The T6L24 offers both low power consumption and high integration circuit due to CMOS technology. Features l LCD drive outputs l Power supply voltage : 240 outputs (80 outputs each for R, G and B) : Digital power supply voltage ...2.7 to 5.5 V Analog power supply voltage ...Max 5.5 V : 2 latches : Bi directional shift register : -20 to 75C : Tape carrier package (TCP) l Sampling method l Data transfer method l Operating temperature l Package l Switching simultaneous/sequential sampling 1 2002-01-07 T6L24 Block Diagram 2 2002-01-07 T6L24 Pin Assignment The above diagram shows the device's pin configuration only and does not necessarily correspond to the pad layout on the chip. Please contact Toshiba or our distributor for the latest TCP specification. 3 2002-01-07 T6L24 Pin Function Pin Name I/O Function Vertical shift data I/O pins These pins are used to input and output shift data. These pins are switched between input and output by setting the U/D pin as shown below: U/D H DI/O DO/I I/O L DI/O Input Output DO/I Output Input When set for input When MODE = low The data is latched into the internal logic synchronously with the rising edge of CPH. The data is sampling in sequentially, starting at the rise of CPH after three clock period. When MODE = high The data is latched into the internal logic synchronously with the rising edge of CPH. The data is sampling in sequentially, starting at the next rise of CPH. When set for output When two or more T6L24s are cascaded, this pin outputs the data to be fed into the next stage. Transfer direction select pin This pin specifies the direction of sampling performed by the sample-and-hold circuit. When MODE = low When U/D is high, data is sampled in the sequence SA1 (R) SB1 (R) SC1 (R) SA2 (R) SB2 (R) x x x (R) SC80 When U / D is low, the sequence is reversed to give SC80 (R) SB80 (R) SA80 (R) SC79 (R) x x x (R) SA1 When MODE = high When U/D is high, data is sampled in the sequence SA1, SB1, SC1 (R) SA2, SB2, SC2 (R) x x x (R) SA80, SB80, SC80 When U/D is low, the sequence is reversed to give SC80, SB80, SA80 (R) SC79, SB79, SA79 (R) x x x (R) SC1, SB1, SA1 Shift clock input This clock sequentially shift the signals necessary to sample the data that are output to the LCD drive output pins (QA1 to QC80). Sample-and-hold switching pin. This pin switches between two sample-and-hold circuits. Sampling mode setting pin. When MODE = high Simultaneously samples three video output signals corresponding to the LCD drive outputs. When MODE = low Sequentially samples the video output signals corresponding to the LCD drive outputs. Analog signal input These pins accept as their input the analog signals that are output to the LCD drive output pins. Sample and hold reference voltage input This is the reference voltage for the sample-and-hold circuit. Apply stable DC voltage to the pin. LCD drive output pins These pins output one of the analog signal inputs (VA, VB and VC) after it has been sampled and held by the sample-and-hold circuit. Power supply for the device's logic block Power supply for the device's high-voltage block Digital GND for the device Analog GND for the device Test pin Use the pin as required. U/D I CPH I CX I MODE I VA VB VC C-COM QA1 to QA80 QB1 to QB80 QC1 to QC80 DVDD AVDD DVSS AVSS TST I I O 3/4 3/4 3/4 3/4 3/4 4 2002-01-07 T6L24 Device Operation (1) Analog signal sampling Data transfer begins with the assertion of DI/O (U/D = high) or DO/I (U/D = low). A high on DI/O is latched into the internal logic synchronously with the rising edge of CPH, and the analog signal to be output to (SA1, SB1, SC1) is sampled at next rising edge of CPH. In this way, all analog signals are sampled of each three channel sequentially at the rising edge of CPH and so on, and the analog signals are output to (SA2, SB2, SC2), (SA3, SB3, SC3) and so on. After the device finishes sampling the data for (SA80, SB80, SC80), it automatically enters standby state. Unless DI/O is asserted again, no data is sampled, irrespective of whether CPH are input to the device. When MODE = high, U/D = low A high on DO/I is latched into the internal logic synchronously with the rising edge of CPH, and the analog signal to be output to (SA80, SB80, SC80) is sampled at next rising edge of CPH. In this way, all analog signals are sampled of each three channel sequentially at the rising edge of CPH and so on, and the analog signals are output to (SA79, SB79, SC79), (SA78, SB78, SC78) and so on. After the device finishes sampling the data for (SA1, SB1, SC1), it automatically enters standby state. Unless DO/I is asserted again, no data is sampled, irrespective of whether CPH are input to the device. A high on DI/O is latched into the internal logic synchronously with the rising edge of CPH, and the analog signal to be output to SA1 is sampled at the rising edge of CPH after three clock period. In this way, all analog signals are sampled sequentially at the rising edge of CPH and so on, and the analog signals are output to SB1, SC1, SA2, SB2, SC2, SA3, SB3, SC3 and so on. After the device finishes sampling the data for SC80, it automatically enters standby state. Unless DI/O is asserted again, no data is sampled, irrespective of whether CPH are input to the device. When MODE = low, U/D = low A high on DO/I is latched into the internal logic synchronously with the rising edge of CPH, and the analog signal to be output to SC80 is sampled at the rising edge of CPH after three clock period. In this way, all analog signals are sampled sequentially at the rising edge of CPH and so on, and the analog signals are output to SB80, SA80, SC79, SB79, SA79, SC78, SB78, SA78 and so on. After the device finishes sampling the data for SA1, it automatically enters standby state. Unless DO/I is asserted again, no data is sampled, irrespective of whether CPH are input to the device. 5 2002-01-07 T6L24 (2) LCD drive output The T6L24 has two sample-and-hold circuits called Sample-And-Hold (1) and (2). These two circuits alternate between serving as the output and the sample-and-hold. Which circuit fulfils which function is determined by the setting of the CX pin. CX L H Output Sample-and-hold circuit (1) Sample-and-hold circuit (2) Sample-and-Hold Sample-and-hold circuit (2) Sample-and-hold circuit (1) The analog signal inputs VA, VB and VC are output as follows: VA is sent to the LCD driver output pins SC1 to SC80, VB is sent to output pins SB1 to SB80, and VC is sent to output pins SA1 to SA80. The analog signal inputs will be sent to LCD driver output pins by the setting of the CX pin as shown below: Note: The CX pin setting must not be altered while the device is sampling data. (3) Vertical shift data output When MODE = high The output DO/I (U/D = high) or DI/O (U/D = low) is driven high for one clock period synchronously with the rising CPH, one clock period before the data (which is to be output to (SA80, SB80, SC80) or (SA1, SB1, SC1)) is latched into the shift register. When MODE = low The output DO/I (U/D = high) or DI/O (U/D = low) is driven high for one clock period synchronously with the rising CPH, one clock period before the data (which is to be output to SA80 or SC1) is latched into the shift register. When using two or more of these devices to drive a large screen, connect the vertical shift data output from the first stage of the LCD driver directly to the vertical shift data input at the next stage. In this way, the device's LCD drive output pin can easily be expanded as necessary. (4) Sample-and-hold reference voltage (C-COM) The device's sample-and-hold circuits are configured using the internal capacitors. The C-COM pin is used to supply the reference voltage for these circuits. Apply stable DC voltage to the pin. 6 2002-01-07 T6L24 Timing Diagram Simultaneous sampling (MODE = high) 7 2002-01-07 T6L24 Sequential sampling (MODE = low, U/D = high) Sequential sampling (MODE = low, U/D = low) 8 2002-01-07 T6L24 Absolute Maximum Ratings (AVSS = DVSS = 0 V) Parameter Supply Voltage (1) Supply Voltage (2) Digital Input Voltage Reference Analog Voltage Storage Temperature Symbol DVDD AVDD VIN VID Tstg Rating -0.3 to 6.5 -0.3 to 6.5 -0.3 to DVDD + 0.3 -0.3 to AVDD + 0.3 -55 to 125 Unit V V V V C Relevant Pin 3/4 3/4 (Note 1) (Note 2) 3/4 Recommended Operating Conditions (AVSS = DVSS = 0 V) Parameter Supply Voltage (1) Supply Voltage (2) Reference Analog Voltage Operating Temperature Operating Frequency MODE = high MODE = low Symbol DVDD AVDD VID TOP fCLK fCLK CL CIN Rating 2.7 to 5.5 DVDD to 5.5 0.2 to AVDD - 0.2 -20 to 75 0.5 to 15 0.5 to 30 50 (max) 10 (max) Unit V V V C Relevant Pin 3/4 3/4 (Note 2) 3/4 3/4 3/4 3/4 3/4 3/4 3/4 pF/PIN pF Output Load Capacitance Input Capacitance Electrical Characteristics DC Characteristics Parameter Low Level Input Voltage High Level Low Level Output Voltage Output Offset Voltage Input Current Current Consumption (1) Current Consumption (2) High Level VIH VOL VOH VOFF IIN DIDD AIDD 3/4 3/4 3/4 3/4 3/4 (DVDD = 3.0 0.3 V, AVDD = 5.0 0.5 V, AVSS = DVSS = 0 V, Ta = -20 to 75C) Symbol VIL 3/4 Test Circuit Test Conditions Min 0 0.8 DVDD 0 VDD 0.3 V -20 -1 3/4 3/4 Typ. Max 0.2 DVDD DVDD 0.3 DVDD V mV A mA mA DI/O, DO/I SA1 to SC80 (Note 1) DVDD AVDD Unit Relevant Pin 3/4 3/4 IOL = 40 mA IOL = -40 mA 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 V (Note 1) 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Note 1: All input pins except the analog signal input pins (VA, VB, VC) Note 2: Analog signal input pins (VA, VB, VC) 9 2002-01-07 T6L24 AC Characteristics (DVDD = 3.0 0.3 V, AVDD = 5.0 0.5 V, AVSS = DVSS = 0 V, Ta = -20 to 75C) Parameter Operating Frequency CPH Pulse Width H CPH Pulse Width L Data Set-up Time Data Hold Time CX Set-up Time Output Delay Time 1 Output Delay Time 2 Output Delay Time 3 Symbol fCPH (1 / tCPH) tCWH tCWL tDSU tDHD tpdC tpdDO tpdDS tpdDX Test Circuit 3/4 Test Conditions MODE = low MODE = high Min 0.5 0.5 Typ. Max 30 15 Unit MHz ns ns ns ns CPH period ns s s 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 CL = 30 pF 3/4 3/4 3/4 3/4 3/4 12 12 5 5 5 3/4 3/4 3/4 3/4 3/4 16 8 15 3/4 3/4 3/4 CL = 50 pF Target output voltage (90%, 10%) CL = 50 pF, Target output voltage 10 2002-01-07 T6L24 11 2002-01-07 T6L24 RESTRICTIONS ON PRODUCT USE 000707EBE * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 12 2002-01-07 |
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